Vsd - Riscv : Instruction Set Architecture (Isa) - Part 1B

[LeeAndro]

Last updated 2/2019MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHzLanguage: English | Size: 528.78 MB | Duration: 2h 52m

Computers are famous for being able to do complicated things starting from simple programs - Let's find out HOW​

What you'll learn
Understand RISC-V architecture in greater detail, and, as per speculations, this is the architecture which you will find in almost 1 trillion mobile devices
Learn how computers and processors does basic calculations
This course will help understand why RISC-V is the next big thing
This course lays the foundation to do RISC-V software basic labs

Requirements
You should have completed RISC-V ISA Part 1a online course
You should be familiar with boolean addition and subtraction concepts
You should be familiar with number systems

Description
pre-launch with 5 videos
This course is in continuation with my previous course "VSD - RISCV : Instruction Set Architecture (ISA) - Part 1a" which dealt with RV64I integer instructions. We also looked at a sample program coded in RISC-V assembly language and viewed the contents of all 32 registers present in RISC-V architecture.
All concepts viewed in Part 1a form the basis of this course and viewer is expected to cover Part 1a course atleast 70%. This course deals with some advanced topics of multiply extension (RV64M) and floating point extension (RV64FD) of the RISC-V architecture - An important one needed in today's fast chag computing world.
We also have explored some facts about hardware, which is the basis of next course (to be launched soon) where we will code the RISC-V ISA using verilog.
So let's get started - again....Happy Learning
Acknowledgements -

I would like to Thank SiFive, a company that was founded by the creators of RISC-V ISA.
I would also like to Thank Prof. David Patterson and his book "Computer Organization And Design - RISCV edition" which immensely helped in the making of this course.
Let's get inside computers...

Overview
Section 1: Introduction

Lecture 1 Introduction

Section 2: Overflow conditions for signed addition and subtraction

Lecture 2 Signed addition and overflow condition for 4-bit word

Lecture 3 Derived overflow conditions for signed addition

Lecture 4 RISC-V overflow checking program for signed addition

Lecture 5 Signed subtraction using addition hardware for 4-bit word

Lecture 6 Overflow condition and conclusion for signed subtraction

Section 3: RV64M - Multiply extension instruction set

Lecture 7 Multiplication algorithm for 4-bit integers

Lecture 8 'mulh' and 'mul' commands to store 128-bit product

Lecture 9 Class-room division method and initialize registers

Lecture 10 Division algorithm initiated

Lecture 11 Conclude results of division algorithm

Section 4: Single and double precision floating point extension - RV64F & RV64D

Lecture 12 Normalized scientific notation of decimal and binary number

Lecture 13 Introduction and need of IEEE754 floating point standard

Lecture 14 Sorting problem with existing floating point representation

Lecture 15 Biased floating point representation

Lecture 16 Floating-point standard conclusion

Section 5: RV64F and RV64D floating point addition & multiplication

Lecture 17 Decimal floating-point addition algorithm development

Lecture 18 Binary floating-point addition and significance of RV64D over RV64F

Lecture 19 Block diagram of floating-point ALU

Lecture 20 Decimal floating-point multiplication algorithm development

Lecture 21 Binary floating-point multiplication and significance of RV64D

Anyone who wants to learn world's first Open-Source instruction set architecture RISC-V,Anyone who wants to learn how to write specifications for RTL coding,Anyone looking forward to implement their own processor using all open-source tools

HomePage:

https://www.udemy.com/course/vsd-riscv-instruction-set-architecture-isa-part-1b/

DOWNLOAD

https://1dl.net/toczqhccdoy2/DwieNTDt__VSD_RISCV_.rar