Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

[LeeAndro]

Video: .mp4 (1280x720, 30 fps(r)) | Audio: aac, 48000 Hz, 2ch | Size: 1.57 GB
Genre: eLearning Video | Duration: 34 lectures (5 hour, 13 mins) | Language: English

Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems.

What you'll learn

Describe and explain VHDL syntax and semantics

Create synthesizable designs using VHDL

Use Xilinx FPGA development board for hand-on experience

Design simple and practical test benches in VHDL

Use the Xilinx Vivado toolset

Design and develop VHDL models

Requirements

Familiarity with digital logic design, electrical eeering, or equivalent experience

Description

Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications.

At the end of this course, participants will be able to accomplish the following:

Describe and explain VHDL syntax and semantics

Create synthesizable designs using VHDL

Use Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experience

Use the Xilinx Vivado toolset

Design simple and practical test-benches in VHDL

Design and develop VHDL models

Prerequisites:

Familiarity with digital logic design, electrical eeering, or equivalent experience.

Even if you're now already familiar with VHDL but you've:

Never used an attribute other than 'event?

Never used variables?

Always used a process where a single concurrent statement would have sufficed?

Never used assert or report statements except (maybe) in a test-bench?

Never used an unconstrained vector or array?

Never used a passive process inside of an entity?

Never used a real or the math_real library package in synthesizable code?

Always used a single process per signal assignment?

then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable.

Who this course is for:

Eeers

Hobbyists

Makers

Eeering Students

Eeering Managers



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